Digital integrated circuit chips are composed of many millions of gates that make up various functional components on a chip such as flip-flops, multiplexers, logic circuits, etc. a given chip design may have thousands of flip-flops scattered throughout the chip.
In order to effectively and efficiently test a given chip, certain test features are typically incorporated into the chip design for testing purposes. Before a chip is actually taped out and manufactured, the chip design is first simulated in software using various simulation tools such as, for example, a Verilog Test Bench. By simulating the design of the chip, the design features of the chip may be thoroughly tested before the expense and time of actually manufacturing the chip is incurred.
Pattern verification is a critical phase in testing of chips. A scan pattern is a digital string of binary ones and zeros that may be shifted through a scan chain of flip-flops in the chip design. Every scan pattern cycle is composed of two phases. The first phase is the load_unload phase where new data is shifted into the scan chains of flip-flops. The second phase is the capture phase where the data is captured into the flip-flops by adding a clock pulse.
Chip designs contain much logic circuitry (logic clouds) around memory circuits. The memory circuits are often bypassed during testing of the design during simulation in order to efficiently test data paths that inlcude the logic clouds around the memory circuits. Testing data paths while including the memory circuits may be difficult because the memory circuits often comprise large arrays of elements.
FIG. 1 illustrates a part of a chip design 5 comprising a memory-bypass-logic circuit 40 used to bypass a memory circuit 30 of the chip design during a scan test mode of the simulation. Typically, a global scan-test-mode signal 45 is used to select the bypass path throgh the memory-bypass-logic circuit 40. The global scan-test-mode signal is driven by a test staion that puts the simulation in the scan test mode. The global scan-test-mode signal is used throughout the design during the scan test mode.
Referring to FIG. 1, data is shifted through a first flip-flop 10 and passes through a first logic cloud 20. The data out of the first logic cloud 20 (i.e., input data to the memory circuit 30) is captured in the memory-bypass-logic circuit 40 and passed to the output logic cloud 60 on the output side of the memory circuit 30, thus bypassing the memory circuit 30 during testing of the scan path.
It is desirable, however, to test certain critical paths through the chip design, which contain memory circuits, during simulation in a path-delay test mode in such a way that memory bypass capability is still supported.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.